1. Field of Invention
The present invention relates to a method of fabricating a substrate. More particularly, the present invention relates to a method of fabricating a substrate with an embedded component therein.
2. Description of Related Art
Generally speaking, a circuit substrate is mainly formed through alternately stacking a plurality of patterned circuit layers and dielectric layers, wherein the patterned circuit layers are defined and formed through a lithography and etching process on copper foils, and the dielectric layers are arranged between the patterned circuit layers for isolating two adjacent patterned circuit layers. Additionally, the adjacent patterned circuit layers are electrically connected through plated through holes (PTH) or conductive vias penetrating the dielectric layers. Finally, various electronic components (such as active or passive components) are arranged on the surface of the circuit substrate, and the purpose of electrical signal propagation is achieved through the circuit design of internal circuits.
However, in order to satisfy the requirements of light weight, thinness, shortness, smallness, and convenience in carrying on electronic products in the market, during the process of manufacturing current electronic products, an electronic component which was originally welded onto the surface of a circuit substrate now may be designed as an embedded component inside the circuit substrate, so as to increase the wiring area in the surface of the circuit substrate and achieve the thinness of electronic products.
FIGS. 1A-1E are schematic sectional views of a conventional fabricating flow of a substrate with an embedded component therein. Firstly, referring to FIG. 1A, a core layer 110 including a first dielectric layer 112, a first patterned circuit layer 114, and a second patterned circuit layer 116 is provided. The first patterned circuit layer 114 and the second patterned circuit layer 116 are disposed on an upper surface 112a and a lower surface 112b of the first dielectric layer 112, respectively.
Next, referring to FIG. 1B, a through hole Hi is formed in the core layer 110 and an embedded component E is disposed in the through hole H1, wherein the embedded component E has two electrodes E1. Subsequently, Referring to FIG. 1C, a first laminated layer 120 and a second laminated layer 130 are arranged on the first patterned circuit layer 114 and the second patterned circuit layer 116, respectively, wherein the first laminated layer 120 includes a first metal layer 122 and a second dielectric layer 124, the second laminated layer 130 includes a second metal layer 132 and a third dielectric layer 134, and the second dielectric layer 124 and the third dielectric layer 134 face the first patterned circuit layer 114 and the second patterned circuit layer 116, respectively.
Furthermore, referring to FIG. 1D, the first laminated layer 120, the core layer 110, and the second laminated layer 130 are pressed together, and at least one plated through hole (PTH) H2 and a plurality of conductive vias V are formed. The plated through hole (PTH) H2 penetrates the first laminated layer 120, the core layer 110, and the second laminated layer 130, such that the first metal layer 122 and the second metal layer 132 are electrically connected through the plated through hole (PTH) H2. Additionally, the two electrodes E1 of the embedded component E are electrically connected to the first metal layer 122 and the second metal layer 132 respectively through the conductive vias V.
Finally, Referring to FIGS. 1D and 1E, the first metal layer 122 and the second metal layer 132 are patterned to form a first surface circuit 122′ and a second surface circuit 132′, which are electrically conducted by the plated through hole (PTH) H2. Furthermore, the two electrodes E1 of the embedded component E are electrically connected to the first surface circuit 122′ and the second surface circuit 132′ respectively through the conductive vias V. In this manner, the fabricating flow of the substrate with an embedded component therein is completed.
However, regarding the conventional method of fabricating the substrate with an embedded component therein, the embedded component E must be electrically connected to the first surface circuit 122′ and the second surface circuit 132′ through the conductive vias V, with a result that the wiring area of the first patterned circuit layer 114 and the second patterned circuit layer 116 is reduced and further the wiring density of the first patterned circuit layer 114 and the second patterned circuit layer 116 is also reduced. Additionally, the embedded component E must be electrically connected to the first surface circuit 122′ and the second surface circuit 132′ through the conductive vias V, which, however, increases the thickness of the whole circuit substrate and thus the requirements of light weight, thinness, shortness, and smallness on product design cannot be satisfied. Therefore, it is really necessary to improve the conventional method of fabricating the substrate with an embedded component therein.